1. Field of the Invention
The present invention relates to a method of manufacturing an electronic device, particularly, to a method of manufacturing an electronic device such as a semiconductor device, a liquid crystal display device or a printed circuit board, in which the step of forming a plated film is improved.
2. Description of the Related Art
In recent years, a copper wire having a low resistivity has been used in, for example, semiconductor devices. The copper wiring is formed by, for example, the method described in the following. In the first step, a trench or the like is formed in an insulating film above a semiconductor substrate, followed by forming a copper film on the surface of the insulating film including the trench. Then, a chemical mechanical polishing (CMP) treatment is applied to the copper film to permit the copper layer within the trench formed in the insulating film so as to form a buried wiring.
It was customary in the past to form the copper film by the electrolytic copper plating method because the electrolytically plated copper film exhibits high burying properties in a concave portion such as a trench and permits simplifying the manufacturing process so as to lower the manufacturing cost.
In the formation of a copper plated film by the electrolytic copper plating method, however, excess copper plated film is deposited and accumulated in regions other than the trench. FIG. 10 shows the situation. To be more specific, a trench (or a hole) 53 is formed in an underlying film 52 formed on a semiconductor substrate 51, followed by forming a seed layer 54 such as a copper layer on the underlying film 52 including the trench 53. Then, an electrolytic copper plating treatment is applied to the entire surface to permit a copper plated film 55 to be deposited and accumulated on the surface of the seed layer 54. At the same time, a film growth exceeding a uniform film thickness takes place in a region right above the trench 53, with the result that excess copper plated film 56 including a stepped portion is deposited and accumulated on the surface of the underlying film 52 other than the trench 53.
Under the circumstances, it is necessary to remove the excess copper plated film formed in the region other than the trench 53 by the CMP treatment. Naturally, a longer time is required for the CMP process, lower in productivity. What should also be noted is that, where the insulating film is formed of, for example, a low-k film, which is brittle, the degree of freedom and the margin of the process are sacrificed by the CMP treatment applied for a long time. For example, damage is done to the insulating film.
Under the circumstances, a method disclosed in PCT/US99/25656 WO 00/26443 is in which a member such as a polishing pad used in the CMP treatment is brought into contact with a semiconductor substrate that is to be subjected to a plating treatment, and simultaneously with or during the electrolytic plating treatment, the film polishing is carried out intermittently so as to suppress the growth of the film.
However, the prior art publication referred to above teaches no more than a method in which an electrolytically plated film is intermittently polished simultaneously with or during the electrolytic plating treatment. What should be noted is that the method disclosed in the prior art publication referred to above fails to overcome essentially the above-noted problem inherent in the prior art that excess copper plated film having a stepped portion is deposited on the surface of the underlying film other than the trench during the electrolytic plating treatment.